In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality.
An eye pattern, also known as an eye diagram (“data “eye” or “eye”), represents a digital data signal from a receiver that is repetitively sampled and applied to the vertical input (axis), while the horizontal input (axis) represents time as a function of the data rate. The eye diagram allows for evaluation of the combined effects of channel noise and inter-symbol interference on the performance of a baseband pulse-transmission system, and the input data eye is the synchronized superposition of all possible realizations of the signal of interest viewed within a particular signaling interval (referred to generally as the data eye), which for convenience might be referred to generally as a unit interval or “UI”. A data slicer (i.e., a Data Latch) in a SerDes device is used for digitizing an analog signal in the serial data receiver, and is usually set in magnitude and phase to the center of the data eye. Precision of the latch threshold has substantial impact on performance (e.g., error rate, jitter tolerance) of the SerDes device.
Current SerDes devices have a fixed termination impedance that may not necessarily be the best termination, even if it is trimmed to 50 ohm (the standard desired termination value) since the characteristic impedance of the channel may not necessarily be 50 ohm. In the current SerDes devices, the termination values in the transmit (TX) and receive (RX) paths are static and are prone to process, voltage and temperature (PVT) variation. A RX termination not matching the channel creates discontinuity at integrated circuit (IC) chip boundaries. Even an ideal 50 ohm termination is not necessarily the optimal termination. A mistuned termination with respect to the channel creates poor return loss and hence degraded receiver operating margin.
In a SerDes RX data path, which includes a variable gain amplifier (VGA), linear equalizer (LEQ), multiplexer (MUX) and combiner (e.g., a H1 SUMMER), the reference bias for each stage is fixed for each stage of RX data path, i.e. bias for each of the VGA, LEQ, MUX and H1 Summer is fixed. The low frequency gain of the RX data path typically has a large variation over PVT. In some systems, about 20 dB gain variation over PVT can be observed for a RX data path. This large variation of low frequency gain adversely affects the performance of a SerDes device.